PCB design rule classification



Item/Image

Description

Letter

Capacity

1.Staggered Microvias (laser drill)

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1.1 Min outer layer microvias

1.2 Min inner layer microvias

1.3 Min distance(micro-vias &edges)

1.4 Min microvias pad

1.5 Max dielectric between microvias layers

A

B

C

D

N

3 mil

3 mil

6 mil

15 mil

≤3 mil

2. Staggered microvia and buried via

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2.1 Min buried via

2.2 Min micro vias

2.3 Min distance (between buried via

     & micro via edges)

2.4 Min buried via pad

2.5 Min micro vias pad

A

B

C


    D

E

8 mil

3 mil

6 mil


        20 mil

12 mil

3. Material & Construction

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3.1 Finished Board Thickness

3.2 Min Inner Layer Thickness

3.3 Min Dielectric Thickness

3.4 Max Inner Layer Copper

3.5 Max Outer Layer Copper

H

H1

H2

T1

T2

8-200 mil

2 mil

2  mil

10 oz

10 oz

4. Warp

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4.1 Max Warp and Twist

AB

<0.75%

5. Pad

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5.1 Min Finished Hole Size

5.2 Min Land Size(as BGA of Pads)

5.3 Min Annular Ring for Vias

5.4 Min Annular Ring for Component

H

R

R1

R1

8 mil

10 mil

4 mil

6 mil

6. Drilling

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6.1 PTH Hole Tolerance

6.2 NPTH Hole Tolerance

A

B

±3 mil

±2 mil

7. Registration for Solder Mask(S/M)

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7.1 Registration for S/M Pattern

7.2 Registration for Legend to S/M

S1/S2

(N/A)

2.5 mil

5 mil

8. Registration for Drill

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8.1 Registration for Drill to Inner Layer

8.2 Registration for Drill To Datum

8.3 Registration for 1st Drill to 2nd Drill

S

S

(N/A)

2 mil

1.5 mil

4 mil

9. Registration for Layers

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9.1 Layer to Layer for 4Layer PCB

9.2 Layer to Layer for 6Layer PCB

9.3 Layer to Layer for 8Layer PCB

S

S

S

3 mil

4 mil

5 mil

10. Line Width

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10.1 Min Inner Line Width(0.5oz)

10.2 Min Outer Line Width(0.5oz)

W2

W1

3 mil

3 mil

11. Line Space

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11.1 Min Inner Layer Space(0.5oz)

11.2 Min Outer Layer Space(0.5oz)

S2

S

3 mil

4 mil

12. Drilling Capacity

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12.1 Max Aspect Ratio

12.2 Min Drill Hole (PCB thickness 78mil

       after plating)

HT

H

10 : 1

8 mil

13. Solder Mask Thickness

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13.1 Max Thickness on Copper

13.2 Max Thickness at Shoulder

H1

H2

0.3-0.7 mil

>0.3 mil

14. Solder Mask Clearance

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14.1 Min Annular Ring

14.2 Min Solder Mask Segment

14.3 Mask Overlap Clearance

14.4 Min Drill Edge to Drill Edge Clearance

MAR

MSM

MOC

DDDEC

2.5 mil

4 mil

2.5 mil

16 mil

15. Carbon Oil Capacity

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15.1 Max Contact Resistance

15.2 Max Primary Resistance

15.3 Min Thickness

15.4 Min Space

15.5 Max Space for Registration

15.6 Min Space for Pad

(N/A)

(N/A)

(N/A)

A

B

C

30Ω/sq

30Ω

4 mil

8 mil

8 mil

8 mil

16. HASL Capacity

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16.1 PCB Thickness for HASL

16.2 Min Pad Width/Space for HASL

16.3 HASL Thickness for Any Point

H2

W

H1

16-158 mil

10 mil

0.2-1.5 mil

17. Outline Tolerance Capacity

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17.1 Outline Tolerance for Punching

17.2 Outline Tolerance for Routing

AB

AB

4 mil

5 mil

18. Beveling Capacity

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18.1 Beveling Angle

18.2 Tolerance   for Outline of Bevel

B

A

20°-60°

±5 mil

19. V-Cut Capacity

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19.1 V-cut Angle V-cut

19.2 Range of Board Thickness

19.3 Tolerance of V-cut Residual

19.4 V-cut Off Line V-cut

C

20°/30°/45°

16-158 mil

±4mil

±4mil

20. Test Capacity

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20.1 Voltage

20.2 Isolation

20.3 Continuity

20.4 Min SMD Part Pitch

(N/A)

(N/A)

(N/A)

P

DC 5-500V

500MΩ

20Ω-100kΩ

12mil

21. Impedance Control Capacity

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21.1 Impedance Control >50Ω

21.2 Impedance Control <50Ω

(N/A)

(N/A)

±10%

±10%

22. Differential Impedance Control Capacity

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22.1 Differential Impedance Control >50Ω

22.2 Differential Impedance Control <50Ω

(N/A)

(N/A)

±10%

±10%

23. Coplanar Impedance Control Capacity

23-23.png

23.1 Differential Impedance Control >50Ω

23.2 Differential Impedance Control <50Ω

(N/A)

(N/A)

±10%

±10%